The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging

Abstract

The era of chiplets and heterogeneous integration is here. High-end performance packaging will be a $7.87 billion market by 2027, with a 19% CAGR. (1)
As the semiconductor industry adopts chiplets and heterogeneous integration for its packaging as a key enabler to the continuation of scaling beyond Moore’s law, it has created new challenges. How will we develop high speed and efficient interconnect protocols? What techniques do we need around post-packaging testing and the quality assurance of the assembled products? How will we monitor the reliability of the die-to-die (D2D) interconnects in mission mode? Emerging solutions are coming to light around how these challenges can be proactively addressed and solved, especially around visibility into high bandwidth D2D interfaces and advanced packaging.

This 40-minute webinar will offer 3 unique perspectives on this growing market and ecosystem:

• Stefan Chitoraga, Technology and Market Analyst at Yole Développement will present the latest market insights on the adoption of chiplets and heterogeneous integration and will address what is driving advanced packaging toward 2.5D and 3D solutions.

• Igor Elkanovich, CTO at Global Unichip Corp. (GUC) will discuss the GUC GLink™ chiplet interconnect, including its architecture and roadmap; the HBM3 memory interface; and will also highlight some of the 2.5D and 3D packaging challenges.

• Nir Sever, Senior Director of Business Development at proteanTecs will reveal silicon results from a GUC GLink chip, which used D2D interconnect monitoring for comprehensive visibility and parametric lane grading.

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