Navigating Timing Margins Like WAZE

Remember the pre-smartphone days, before navigation apps had our backs?

Thanks to a lack of real-time visibility, ‘arriving early’ was the go-to strategy to avoid arriving late. Factor in too much ‘holdup time’ and you’d arrive a little too early. There’s nothing worse than nervously burning off an excess 30 minutes over a coffee you really didn’t need.

Today you wouldn’t get in your car without turning on a mapping-app like Waze. Nevermind a far unknown journey, you wouldn’t dream of being without it on your simple work commute. The app changed the way we travel by simply giving us more visibility of our own time margins.

Thanks to algorithms lurking beneath Waze’s deceptively simple interface, we’re now adept in optimizing journey times to a ‘Goldie Locks’ standard—arriving neither late nor early, but right on time. We now know the exact ETA based on real-time traffic and road conditions, with optimal route insights. Waze gives us back time by allowing us to efficiently manage our schedules. And time is money.

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Looking at Chip Timing-Margins Through the Waze Lens

Like our journey margins, timing margins in ICs are the actual change (arrival) in a signal and the latest time at which the signal can change (or arrive) for circuits to function correctly. For synchronous systems to work, timing requirements must fit within one clock cycle. In digital designs, it’s the ‘make or break’ of functionality.

It’s important to approach the problem of chip health and performance from a fresh angle. With chip power/performance pushed to the limit, margins become less abundant and expensive; at this point, we can no longer rely on precautionary overdesign to come to the rescue. Particularly, in a landscape that pushes the envelope on competitiveness.

On the other hand, with system reliability required at 24/7 warp speed, there is no room for margin deficiency. Electronics cannot afford to be left empty-handed, with signals arriving “too late” to the party. Chip design is so often governed by a balancing of trade-offs. However, a telemetric approach to the problem is starting to change that.

Recalculating Route with proteanTecs

As with travel apps that continuously monitor transportation paths, chip manufacturers can now access similar ‘real-logic’ monitoring of the millions of paths that signals travel along, while an application is running. For the first time, they can identify the critical paths and the actual remaining margin for each.

In terms of chip development, the potential implications of this are staggering. For the first time, chip manufactures can end their reliance on chip design that adheres to the limitations of worst-case margins. To understand the mechanics behind this game-changing innovation, let’s look at how Waze works its magic.

By turning users’ cell-phones into data collection points, Waze obtains a high coverage spread of ‘feet-on-the-ground’ measurements. By deploying this telemetric method, Waze is able to provide turn-by-turn navigation that sources and monitors information through machine learning algorithms to build a ‘big picture’ that's widespread and high resolution. Users are empowered to make reliable, data-driven decisions that optimize their time allocation.

Going ‘Street Level’ with IC Margin Visibility

To overcome the lack of margin visibility in production and in-field, proteanTecs is taking a new approach. Deep Data analytics, based on chip telemetry, gives manufacturers a Waze-like way of monitoring signal traffic along a chip’s critical paths.

Embedded on-chip Agents become high coverage, wide-ranging measurement points whose readouts feed powerful machine learning algorithms, to build a granular picture of chip conditions and margins. Suddenly, chips are able to report on their own health metrics via advanced analytics, as they navigate from fabrication through to active use.

The upshot of gaining visibility into the timing margins at every turn are many:

In-production benefits for manufacturers and OEMs:

• Tighter guard bands mean improved yields
• Post-to-pre silicon correlation enabling chip design validation
• Margin can be designed to reliably meet DPPM targets
• Performance grading of new devices  
• Performance degradation monitoring during Accelerated Lifetime Tests

In-field benefits for brand owners and service providers:

• A quantitative view of how margins degrade or fluctuate over time
• Alerts on faults before failure for predictive maintenance

For value chain stakeholders this means a competitive seat at the wheel with a view on in-the-moment and over-time changes in the chip’s timing margin, a first-row view on opportunities for production optimization, and a total transformation of maintenance during use from preventive to predictive—all driven by telemetry and reported in an analytics dashboard view.

It’s perhaps overdue, but chip manufacturing is finally catching up with innovations that have become par for the course even in our every-day lives. We’re confident that, before long, we’ll be reflecting on our soon-to-be outdated methods in the same way we reflect on map and compass navigation.